DC-DC converters are common circuits used in modern electronics for the purpose of supplying a DC voltage at one level from another. These are particularly useful building blocks for the ever growing popularity of battery powered or cordless devices. Typical integrated circuit components require a power supply of 3.3 volts or more. A typical alkaline battery cell will have a starting voltage of near 1.5 v and will have an end of life voltage about 1.1V. The DC-DC converter provides two important functions. The first is to step up the battery voltage from the 1.5V battery power range to the 3.3V range, and the second is to compensate for the normal 25% drop of the battery voltage and still supply a stable 3.3V to the device electronics. These basic functions are somewhat taken for granted in the DC-DC converter marketplace, and focus has shifted to ever increasing demand for prolonging battery life though the pursuit of a highly-efficient, ultra-low power DC-DC converters. DC-DC converters are commonly described as “buck” if the output level is lower than the input voltage, “boost” if the output level is higher than the input voltage, and “buck-boost” if the converter can provide an output voltage from a variety of input voltage levels. The DC-DC converters require control circuitry and methods to maintain the output voltage at a determined level, and in low power converters, all can benefit from a “sleep” or standby mode where the power consumed is reduced during periods of no demand from a load coupled at the output.
In pursuit of highly efficient, ultra-low power DC-DC converters, two characteristics are particularly relevant. The first and primary differentiator is low power consumption and in particular, low standby current or quiescent current (Iq). In low power converter operation, Iq is the limiting factor in improving the converter efficiency. Iq is the current used by the DC-DC converter when the converter is on, but there is little or no load current demanded by the device. This condition is typically present during an operational state termed “sleep mode”. The lower the power consumption in sleep mode, the longer batteries in the device will generally last between charges, since sleep mode is the predominant mode for many battery powered devices.
The second characteristic is transient output voltage regulation. The quality of the output voltage regulation during load transients is specified by two parameters: Vdip and Vrec. Vdip is the variation between the desired output voltage and the actual output voltage (Vout) when a fast transient load occurs during the sleep mode. Vout recovery slew rate (Vrec) indicates how quickly a DC-DC converter is able to recover from a Vdip event. These two parameters, Vdip and Vrec, help determine the quality of the transient load regulation. Improving the converter performance for these transient parameters is usually at odds with the additional goal of maintaining a low Iq for a DC-DC converter. The opposing relationship between these design parameters will be described in the following example.
A battery powered cordless mouse is a common consumer device that will serve as an illustrative, non-limiting example application. Within the example mouse, a single battery or battery pack feeds a DC-DC power converter, which in turn supplies 3.3V power to the rest of the mouse movement and transmission electronics. When the mouse is switched on, yet is sitting idle on a desk for example, the mouse electronics goes into an inactive mode where the mouse electronics are using as little power as possible, while waiting to detect movement. During this time, the DC-DC converter maintains the mouse electronics voltage at the 3.3V level while it can also conserve power by operating in its “sleep mode”. The inactive mode is the predominant mode of a battery powered mouse and the sleep mode is the predominant mode for the low power DC-DC converter, hence the focus on low standby current, Iq, in DC-DC converters.
FIGS. 1A and 1B show in a pair of graphs the voltage decay and error in a sampled or clocked DC-DC converter. In FIG. 1A, graph 100 illustrates voltage on the vertical axis and time on the horizontal axis. Graph 100 plots the desired output voltage (Vref1), the sample clock (Cs) and the actual output voltage (Vout2). Graph 100 illustrates the predominant mode, where in the example mouse the electronics would be considered to be in a steady state low power mode. In this mode the device load is very low, causing the decay of the output voltage Vout2 to decrease very gradually, as illustrated in the time period labeled 108. To save power in the sampled DC-DC converter, the sample clock Cs period is extended to a maximum time interval between pulses labeled 110. During the voltage decay, the sample clock Cs triggers a comparator to inspect the converter output voltage VOUT2 at the intervals 110. At the end of period 108, the VOUT2 error 106 reaches a lower threshold, which triggers the DC-DC converter to become active and increase the output voltage VOUT2. After the DC-DC converter is enabled following the trigger event, the output voltage begins rising to a level 104 which is slightly above the desired Vref1 level. It is important to note that during the time periods 108 while the output voltage is gradually decaying, the DC-DC converter may be in its sleep mode and the sample interval 110 is much longer than the sample interval used during an active supply mode. In sleep mode the sample interval is increased so as to further conserve power. The current consumed by the DC-DC converter in periods when the device is using very little power (Iq) is the characteristic that helps extend the life of the batteries. A lower Iq is desired to further extend the battery life. By extending the time between samples, the standby power is further reduced.
In the example mouse, when the mouse is moved, the electronics are set into action and a much heavier current load is suddenly placed on the output voltage and the battery, as movement data is detected and transmitted during a mode that will be called “active mode”. In FIG. 1B a sample graph 120 is presented with voltage on the vertical axis and time on the horizontal axis, and plots the desired output voltage (Vref1), the sample clock (Cs) and the actual output voltage (Vout2) during active mode. Graph 120 illustrates typical voltage trends and sample clock for a DC-D converter during active use. In graph 120, the voltage decay at the output is much steeper, as illustrated during period 128, when compared to the decay in time period 108 shown in graph 100. Because of this faster decay time, the sample clock period Cs is shortened (the clock frequency is increased) to a minimum time interval between clocks 130 so that voltage regulation is improved and the allowable voltage error 126 is not exceeded. Having reviewed the steady state cases, sleep mode and active mode, the transition from sleep mode to active mode will now be described to illustrate the importance of output voltage regulation during transients, and to show why the sample clock Cs cannot be arbitrarily set to a very long interval.
FIG. 2 presents in a sample graph 200 a transient output voltage and sample clock change in a low power DC-DC converter. In FIG. 2, sample graph 200 is shown with voltage on the vertical axis and time on the horizontal axis and plots the desired output voltage (Vref1), the sample clock (Cs) and the actual output voltage trends (VOUT2). In graph 200, the time period 208 is a lightly loaded or sleep mode region, while time period 210 depicts a transition period where the sample clock interval becomes successively smaller in response to an increased load at the output, and time period 212 show a period where Cs has decreased to a minimum interval in an active mode region.
In sampled DC-DC converter designs, the parameters Vdip and Vrec are general indicators of the quality of voltage load regulation and are usually inversely proportional to the standby current Iq. The worst case Vdip generally occurs under the condition where the DC-DC converter is in sleep mode and a heavy load is applied at the output just after a Cs clock edge. In that event, illustrated in graph 200 at point 204, the output voltage Vout will begin a steep decline. When the next Cs sample occurs, illustrated at point 206, the voltage error is detected and the DC-DC converter is enabled to correct Vout. The difference between the desired voltage Vref1 and the lowest output voltage point 206 is defined as the characteristic Vdip. In a commercially available best-in-class low power DC-DC converter, the Vdip is specified as 37 mV. Furthermore, the recovery characteristic Vrec is the slew rate that the Vout achieves in recovering from Vdip. In graph 200, Vrec would be the delta voltage 220 divided by the time to recover 222 and in the same best-in-class low power DC-DC converter described previously, the Vrec is specified as 0.5 mV/microsecond (μSec). (In an ideal converter, the Vdip would be zero and the Vrec would be infinite, however in a practical design the ideal is not possible.)
Furthermore, the competing goals of low power during sleep mode and transient output regulation can be illustrated by this example shown in graph 200. If better output voltage regulation is desired, that could be accomplished by increasing the sleep mode Cs frequency (shorter Cs time intervals), however that in turn increases the sleep mode power consumption. Conversely, if a lower sleep mode power is desired, reducing the frequency of the sleep mode Cs clock would accomplish that goal, however it comes at the expense of the Vout falling to a lower level before correction begins (larger Vdip), thus making load regulation worse. In the DC-DC converters of the prior known solutions, these parameters present a design trade-off, as lower quiescent current Iq cannot be obtained while also improving Vdip and Vrec.
FIG. 3 is a circuit block diagram 300 of a low power, sampled DC-DC converter using a prior known approach. In 300, four sections, numbered 302, 304, 306 and 308, denote components that are active in common operational times. The first section 302 contains a digital control block 310 which receives three signals, an enable signal En1, a sample clock Cs and the output voltage Vout. The digital control block 310 is coupled to an oscillator 312. The oscillator receives as input the voltage VOUT and outputs the sample clock (Cs) which is fed back to the digital control 310 and into a clock comparator 322 in section 304. In section 304 a system reference 320 outputs a reference voltage Vref which is coupled to clock comparator 322. The clock comparator also receives voltage VOUT and the sample clock Cs from the oscillator 312.
An enable signal (En) is output by the clock comparator and is coupled to the digital control 310 in section 302 and to the DC-DC converter in section 306. In section 306 a DC-DC converter 330 receives an enable signal (En) from comparator 322 and an input voltage VIN to be converted to the output a voltage VOUT. The VOUT is coupled to a load 340. Additionally, the output voltage VOUT is coupled back as a feedback signal for use in sections 302 and 304 as previously described. The load 340 includes an output capacitance, and an impedance.
In this example prior known approach low power DC-DC converter, section 302 is always actively drawing power, with the digital control section 310 counting the enable signals En and adjusting the frequency rate at which the oscillator 314 outputs sample clocks Cs. The oscillator frequency is increased with increasing numbers of En signals (indicating additional demand from the load) and decreased with fewer En signals (indicating reducing demand from the load) in a given time period. The result is a varying Cs frequency, such as is illustrated by the plots of a Cs signal in FIG. 1 and FIG. 2. Section 304 is only powered when a sample clock Cs is active. In section 304 a reference voltage is provided by a system ref block 320. Vref is compared to the VOUT at comparator 322 and if VOUT is less than Vref, an enable signal (En) is generated. At that point, these 2 components turn off until the next sample clock Cs arrives, thus conserving power. A stand-alone control section 305 consists of section 302 and 304 as illustrated and within that control section outputs an enable signal for a DC-DC converter receives the output voltage VOUT.
Section 306 contains a DC-DC converter 330 that performs the DC-DC voltage conversion when the enable signal is active. The output signal VOUT could operate as illustrated by the plots of VOUT2 in FIG. 1 and FIG. 2. Section 308 contains sample load 340.
FIG. 4 depicts in a block diagram 400 additional details of an example implementation for the control functions of the circuit 300 of FIG. 3. In FIG. 4, for convenience of explanation, the lower digits of the blocks 412, 410, 422 are the same as the lower digits for the corresponding blocks 312, 310, 322 in FIG. 3. In FIG. 4, the oscillator 412 is shown implemented, in a non-limiting example, as a current-capacitor or I/C oscillator, with weighted current sources charging a capacitor to form a clock pulse. A control input labeled CNTRL (n:0) provides a thermometric control code to enable the current sources. A sample clock is used to enable a clocked comparator 422 that compares a feedback of the output voltage, labeled Vfb, to a reference voltage level and outputs an enable signal En when the output voltage is below the reference level and the clock Cs is active.
A digital controller 410, which corresponds to the controller 310 in FIG. 3, can be used to control the frequency of the adjustable oscillator 412. In FIG. 4, a possible implementation is shown, however the arrangements of the present application can also use alternative arrangements to implement the controller. In FIG. 4, a counter 450 counts the clocks between enable signals output from the comparator 422. The controller 410 uses a pair of comparators 452, 454 that each compares the number of enable signals, or KICK signals, counted over a time period to a maximum and a minimum level. If the number of clocks counted between the KICK signals is too high, greater than the maximum as indicated by comparator 454, a count is decremented in block 458, and the oscillator frequency is reduced. If the number counted is below a minimum as indicated by comparator 452, the counter in block 458 is incremented, and the frequency is increased. In this manner the oscillator 412 is dynamically adjusted by controller 410 to keep the output voltage Vout within certain error ranges, while simultaneously reducing power when demand at the load is low.
A sampled DC-DC converter as illustrated by block diagram 300 can generate waveforms similar to those described in FIG. 1 and FIG. 2. The principal function of the control circuitry in section 305 is to make the entire DC-DC conversion process consume as little power as possible when it is in a sleep mode, while also providing acceptable load regulation in response to current demanded by the load on the Vout terminal. The low power consumption corresponds to having a small Iq, small Vdip and a fast Vrec. As explained above, when using prior known approach converters, improvements in transient response performance (improvements in Vdip and Vrec) conflicts with additional improvements in the Iq current.
Therefore, continuing improvements are needed in methods and apparatus for low power, low Iq, fast transient response in DC-DC converters. Aspects of the present application will improve upon the prior known approaches in providing low power sampled DC-DC converters and corresponding control circuitry and methods.